Interconnect Architecture Exploration for Low-Energy Reconfigurable Single-Chip DSPs

In this paper, we present and analyze a number of interconnect architectures for reconfigurable systems targeting applications in the areas of wireless communication and multimedia processing. Several interconnect architectures suitable for heterogeneous elements are proposed and then a methodology to evaluate the architectures is described. The results indicate that the hierarchical generalized mesh structure shows the most promise in terms of energy efficiency, as it can optimize both local and global connections.